ECET 330 Lab 1 Part 1 Procedures Title Introduction to Memory Map I

ECET 330 Lab 1 Part 1 Procedures Title Introduction to Memory Map I


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ECET330 Lab 1 Part 1 Procedures

Title: Introduction to Memory Map



1. To become familiar with address decoding

2. To become familiar with HCS12 memory map


IBM PC, or compatible with Windows 2000 or higher


For the CPU to process information, the data must be stored in RAM or ROM. ROM is a type of memory that does not lose its contents when the power is turned off. Different types of ROM are PROM, EPROM, EEPROM, Flash EPROM, and mask ROM. The CPU is connected to RAM and ROM using the address bus, data bus, and control bus.

RAM: Stands for random access memory; refers to memory that the microprocessor can read from and write to. Program variables and data as well as stack data storage are saved in RAM of the microcontroller.

ROM: Stands for read-only memory. The microcontroller can read from ROM, but it can’t write to or modify it.

EEPROM: One type of ROM is EEPROM, which is Electrically Erasable Programmable ROM. Variables that must remain when the power is turned off are stored in EEPROM.

Flash memory: A special type of memory that works like both RAM and ROM. You can write information to flash memory, like you can with RAM, but that information isn’t erased when the power is off, like it is with RAM. All program code, constants such as messages and lookup tables, and any other information that does not change, are saved in flash memory of the microcontroller.



The programs for an embedded system must be in read-only memory, and thus we must know something about the hardware upon which our software is installed. For example, we need to know the memory location where the code or data should reside. Figure 1 shows the block diagram of HCS12 microcontroller.



1. Figure 1 below shows a given CPU connected to two 8Kx8 SRAM units, one 16Kx8 SRAM unit, and a 32Kx8 SRAM unit. Address lines A13, A14, and A15 are used to select one of the memory units. Looking at the figure below, complete the Table 1 that represents the memory map of Figure 1.

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