ECET 230 ECET230 Week 6 Homework Solution

ECET 230 ECET230 Week 6 Homework Solution

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ECET 230 Homework Assignment 6

1.The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses, the register contains:

(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101

2. With a 100 kHz clock frequency, eight bits can be serially entered into a shift register in:

(a) 80 ms (b) 8 ms (c) 80 ms (d) 10 ms

3. For a 10-bit serial-in/serial-out shift register, determine Data out for the Data in and clock waveforms shown below. Assume that the register is initially cleared.

4. Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the shift register specified in Problem 3. Verify the timing diagram shown in Problem 3. Attach the .vhd and simulation files.

5.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the 74LS194A universal, bi-directional shift register. Attach the .vhd and simulation files.

6.In your own words, explain the purpose of concatenation in a VHDL signal assignment.

7. Develop the state diagram for a MOD-4 counter with an even number count sequence: 000, 010, 100, 110, 000, etc. All undefined states must return to 000.


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